74hc138


74hc138

Vu sur patty-a.com

wide supply voltage range from .v to .v. •. sinks or sources ma at vcc = .v. •. cmos low power consumption. •. schmitt trigger action at all inputs. •. inputs accept up to .v. •. esd protection tested per jesd . •. exceeds v machine model (aa). •. exceeds v human body model (aa).

74hc138

Vu sur dojft4652t1in.cloudfront.net

hc; hct. to line decoder/demultiplexer; inverting. rev. — march . product data sheet. general description. the hc; hct decodes three binary weighted address inputs. (a, a and a) to eight mutually exclusive outputs (y to y). the device features three enable inputs (e, e 

74hc138

Vu sur forum.allaboutcircuits.com

the mchca is identical in pinout to the ls. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the hca decodes a three−bit address to one−of−eight active−low outputs. this device features three chip select inputs, two active−low 

74hc138

Vu sur piclist.com

high speed cmos logic to line decoder demultiplexer inverting and noninverting. high speed cmos logic to line decoder demultiplexer inverting and non. datasheet. cd/hc, cd/hct, cd/hc, cd/hct datasheet (rev. i) · download. in english, 中文内容 · 日本語表示.

74hc138

Vu sur edaboard.com

to line decoder/demultiplexer. specifications. the mmhc decoder utilizes advanced silicongate cmos technology and is well suited to memory address decoding or data routing applications. the circuit features high noise immunity and low power consumption usually associated with cmos circuitry, yet has 

74hc138

Vu sur circuitdiagramworld.com

the hc; hct is a highspeed sigate cmos device and is pin compatible with lowpower schottky ttl (lsttl). the hc; hct decoder accepts three binary weighted address inputs (a, a and a) and when enabled, provides mutually exclusive active low outputs (y to y). the hc 

74hc138

Vu sur rarecomponents.com

hc, hc datasheet, hc to decoder datasheet, buy hc.

74hc138

Vu sur pdf-datasheet.datasheet.netdna-cdn.com

le hc est un décoder d'adresse démultiplexeur bits vers lignes. vous entrez une adresse binaire sur les broches d'adresses a, a, a et vous avez la broche y à y correspondant qui s'active. sur le hc, les lignes de sortie sont ny à ny, cela signifique qu'elles sont en logique inversée. elles sont 

74hc138

Vu sur technobotsonline.com

the hc/hct decoders accept three binary weighted address inputs (a, a, a) and when enabled, provide mutually exclusive active low outputs (y to. y). the “” features three enable inputs: two active low. (e and e) and one active high (e). every output will be. high unless e and 

74hc138

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